When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
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|PDF 295 KB||Datasheet|
Renesas General-Purpose ICs Power Management Linear ICs / General-Purpose Linear ICs / General-Purpose Logic ICs General CatalogPDF 5.23 MB
|PDF 1.32 MB||Brochure|
|PDF 155 KB 日本語||Datasheet|
Unification of a JEDEC tray and a embossed carrier tape for LQFP package (Additional Information & Correction)PDF 4.86 MB 日本語
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|PDF 3.74 MB 日本語||Product Change Notice|
|PDF 1.46 MB 日本語||Product Change Notice|
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