Overview

Description

When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features

  • High-Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)
  • High Output Current: Fanout of 15 LSTTL Loads
  • Wide Operating Voltage: VCC = 2 to 6 V
  • Low Input Current: 1 µA max
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Documentation

Document title Document type
Type
Date Date
PDF 295 KB Datasheet
PDF 5.23 MB Brochure
PDF 1.32 MB Brochure
PDF 155 KB 日本語 Datasheet
PDF 4.86 MB 日本語 Product Change Notice
PDF 3.74 MB 日本語 Product Change Notice
PDF 1.46 MB 日本語 Product Change Notice
7 items

Design & Development

Models