This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state.

Features

  • High-Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
  • High Output Current: Fanout of 10 LSTTL Loads
  • Wide Operating Voltage: VCC = 2 to 6 V
  • Low Input Current: 1 µA max
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Product Options

Orderable Part ID Part Status Buy Sample
HD74HC273RP
Obsolete
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
HD74HC273 Datasheet 日本語 Datasheet PDF 146 KB
HD74HC Series Common Information Datasheet PDF 295 KB
PCNs & PDNs
Unification of a JEDEC tray and a embossed carrier tape for LQFP package (Additional Information & Correction) 日本語 Product Change Notice PDF 4.86 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 3.74 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 1.46 MB
Other
Renesas General-Purpose ICs Power Management Linear ICs / General-Purpose Linear ICs / General-Purpose Logic ICs General Catalog Brochure PDF 5.23 MB
Renesas Semiconductor Lead-Free Packages Brochure PDF 1.32 MB