The HD74HC240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently controls 4 buffers. This device does not have schmitt trigger inputs.

Features

  • High-Speed Operation: tpd = 10 ns typ (CL = 50 pF)
  • High Output Current: Fanout of 15 LSTTL Loads
  • Wide Operating Voltage: VCC = 2 to 6 V
  • Low Input Current: 1 µA max
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Product Options

Part Number Part Status Buy Sample
HD74HC240RP
Obsolete
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
HD74HC240 Datasheet 日本語 Datasheet PDF 125 KB
HD74HC Series Common Information Datasheet PDF 295 KB
PCNs & PDNs
Unification of a JEDEC tray and a embossed carrier tape for LQFP package (Additional Information & Correction) 日本語 Product Change Notice PDF 4.86 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 3.74 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 1.46 MB
Other
Renesas General-Purpose ICs Power Management Linear ICs / General-Purpose Linear ICs / General-Purpose Logic ICs General Catalog Brochure PDF 5.23 MB
Renesas Semiconductor Lead-Free Packages Brochure PDF 1.32 MB