Features
- Pin to Pin compatible to the higher density IDT72V361x0
- Up to 166 MHz Operation of the Clocks
- User selectable Asynchronous read and/or write ports (PBGA Only)
- User selectable input and output port bus-sizing
- 5V input tolerant
- Auto power down minimizes standby power consumption
- Master Reset clears entire FIFO
- Partial Reset clears data, but retains programmable settings
- Easily expandable in depth and width
- JTAG port, provided for Boundary Scan function (PBGA Only)
- Independent Read and Write Clocks
- Available in 128-pin TQFP or 144-pin PBGA packages
- Industrial temperature range (–40C to +85C) is available
Description
The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
Parameters
| Attributes | Value |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 36 |
| Density (Kb) | 512 |
| Pkg. Code | PKG128 |
| Interface | Synchronous |
| I/O Type | 3.3 V LVTTL |
| I/O Frequency (MHz) | - |
| Organization | 16K x 36 |
| Temp. Range (°C) | -40 to 85°C |
| Architecture | Uni-directional |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 20.0 x 14.0 x 1.4 | 128 | 0.5 |