Overview

Description

The 8A34043 Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI).  The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

Features

  • Four independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • Supports up to 8 differential or 16 single-ended reference clock inputs
  • Supports up to 12 differential outputs or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

Applications

Documentation

Document title Document type
Type
Date Date
PDF 1.79 MB Datasheet
PDF 465 KB Application Note
PDF 199 KB Application Note
PDF 164 KB Application Note
PDF 140 KB Application Note
PDF 84 KB Application Note
PDF 1.92 MB Application Note
PDF 231 KB Application Note
PDF 1.62 MB Application Note
PDF 390 KB Application Note
PDF 880 KB Application Note
PDF 584 KB Application Note
PDF 162 KB Application Note
PDF 976 KB Application Note
PDF 659 KB Application Note
PDF 324 KB Application Note
PDF 38 KB Device Errata
PDF 10.53 MB Guide
PDF 2.35 MB Guide
PDF 213 KB Guide
PDF 143 KB Guide
PDF 1.99 MB Manual - Hardware
PDF 215 KB Manual - Software
XLSX 321 KB Other
PDF 320 KB Overview
PDF 1.83 MB Overview
PDF 135 KB Product Change Notice
PDF 113 KB Product Change Notice
PDF 301 KB Product Change Notice
PDF 123 KB Product Change Notice
PDF 983 KB Product Change Notice
PDF 435 KB Product Change Notice
PDF 164 KB Release Note
PDF 103 KB Release Note
34 items

Design & Development

Software & Tools

Software Downloads

Software title Software type
Type
Date Date
ZIP 51.88 MB Software & Tools - Other
ZIP 18.02 MB Software & Tools - Other
ZIP 278 KB Software & Tools - Other
ZIP 73 KB Software & Tools - Other
ZIP 177 KB Software & Tools - Other
ZIP 177 KB Software & Tools - Other
6 items

Boards & Kits

Boards & Kits

Models

Models

Title Type Type Date Date
ZIP 2 KB Model - BSDL
ZIP 2.55 MB Model - IBIS
2 items

Support

IDT ClockMatrix™ 8A3404x Multi-channel DPLL / DCO Programmable, Sub-150fs Jitter Timing Solution

The ClockMatrix family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

The 8A3404x Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) family provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI).  The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. 

The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces

For more information, visit www.idt.com/clockmatrix.