Evaluation Kit for 8A34003 ClockMatrix
This is the evaluation kit for the 8A34003, 8A34004, 8A34013, and 8A34043. The 8A34003 is functionally a superset of these products, making it suitable to evaluate any...
The 8A34043 Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
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PDF 1.79 MB | Datasheet | |
PDF 247 KB | Application Note | |
PDF 164 KB | Release Note | |
PDF 465 KB | Application Note | |
PDF 199 KB | Application Note | |
PDF 164 KB | Application Note | |
PDF 140 KB | Application Note | |
PDF 215 KB | Manual - Software | |
PDF 84 KB | Application Note | |
XLSX 321 KB | Other | |
PDF 320 KB | Overview | |
PDF 1.92 MB | Application Note | |
PDF 103 KB | Release Note | |
PDF 135 KB | Product Change Notice | |
PDF 10.53 MB | Guide | |
PDF 113 KB | Product Change Notice | |
PDF 2.35 MB | Guide | |
PDF 213 KB | Guide | |
PDF 231 KB | Application Note | |
PDF 38 KB | Device Errata | |
PDF 143 KB | Guide | |
PDF 1.62 MB | Application Note | |
PDF 390 KB | Application Note | |
PDF 880 KB | Application Note | |
PDF 584 KB | Application Note | |
PDF 301 KB | Product Change Notice | |
PDF 162 KB | Application Note | |
PDF 123 KB | Product Change Notice | |
PDF 983 KB | Product Change Notice | |
PDF 1.99 MB | Manual - Hardware | |
PDF 435 KB | Product Change Notice | |
PDF 976 KB | Application Note | |
PDF 659 KB | Application Note | |
PDF 324 KB | Application Note | |
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This is the evaluation kit for the 8A34003, 8A34004, 8A34013, and 8A34043. The 8A34003 is functionally a superset of these products, making it suitable to evaluate any...
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Select an orderable part number:
Orderable Part ID | Sample |
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8A34043E-000NBG | Availability |
The ClockMatrix family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.
The 8A3404x Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) family provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources.
The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces
For more information, visit www.idt.com/clockmatrix.