The ICS85304I-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer. The ICS85304I-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most
standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the ICS85304I-01 ideal for those applications demanding well defined performance and repeatability.


  • Five 3.3V differential LVPECL output pairs
  • Selectable differential CLKx, nCLKx input pairs
  • CLKx, nCLKx input pairs can accept the following differential levels: LVDS, LVPECL, LVHSTL and HCSL levels
  • Maximum output frequency: 650MHz
  • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs 
  • Output skew: 60ps (maximum) 
  • Part-to-part skew: 300ps (maximum)
  • Propagation delay: 2.1ns (maximum)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) package




Design & Development