2-Output 1.8 V PCIe Gen1-4 Clock Generator with Zo=100 ohms
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Overview
Description
The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen1–4 applications with integrated output terminations providing Zo=100 Ω. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
Features
- PCIe Gen1–4 compliant
- Integrated terminations provide 100 Ω differential Zo: reduced component count and board space
- 1.8 V operation: reduced power consumption
- OE# pins: support DIF power management
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- DIF outputs blocked until PLL is locked: clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
- External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
- Configuration can be accomplished with strapping pins: SMBus interface not required for device control
- 3.3 V tolerant SMBus interface works with legacy controllers
- Space-saving 4x4 mm 24-pin VFQFPN; minimal board space
Applications
Documentation
| Document title | Document type
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Date Date | |
|---|---|---|---|
| PDF 316 KB | Datasheet | ||
| PDF 91 KB | Application Note | ||
| PDF 1.99 MB | Application Note | ||
| PDF 255 KB | Application Note | ||
| PDF 307 KB | Application Note | ||
| PDF 480 KB | Application Note | ||
| PDF 235 KB | Application Note | ||
| PDF 1.90 MB | Application Note | ||
| PDF 495 KB | Application Note | ||
| PDF 442 KB | Application Note | ||
| PDF 233 KB | Application Note | ||
| PDF 160 KB | Application Note | ||
| PDF 120 KB | Application Note | ||
| PDF 565 KB | Application Note | ||
| PDF 136 KB | Application Note | ||
| PDF 321 KB 简体中文 | Guide | ||
| PDF 2.40 MB | Overview | ||
| PDF 1.83 MB | Overview | ||
| PDF 734 KB | Product Change Notice | ||
| PDF 728 KB | Product Change Notice | ||
| PDF 726 KB | Product Change Notice | ||
| PDF 2.97 MB | Product Change Notice | ||
| PDF 5.71 MB | Product Change Notice | ||
| PDF 5.61 MB | Product Change Notice | ||
| PDF 983 KB | Product Change Notice | ||
| PDF 583 KB | Product Change Notice | ||
| PDF 361 KB | Product Change Notice | ||
| PDF 27 KB | Schematic | ||
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
Processing table
| VFQFPN | 24 | I | Yes | Tray | Get Samples, | |
| VFQFPN | 24 | I | Yes | Reel | ||
| VFQFPN | 24 | C | Yes | Tray | Get Samples, | |
| VFQFPN | 24 | C | Yes | Reel |
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play_circle_filledVideos & Training
PCIe Reference Clock Jitter Budgets
IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Video List
News & Blog Posts
| Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System | Blog Post | Apr 14, 2022 | |
| Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications | Blog Post | May 22, 2018 | |
| IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices | News | Apr 30, 2018 | |
| IDT Announces World’s Lowest-power PCI Express Timing Family | News | Aug 16, 2012 |
