6-Output 3.3V PCIe Gen1–5 Clock Generator
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Overview
Description
The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen1–5 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRNS) and Separate Reference Independent Spread (SRIS) clocking architectures.
For information regarding evaluation boards and material, please contact your local sales representative.
Features
- PCIe Gen1–5 CC-compliant
- Supports PCIe SRIS and SRNS clocking
- Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
- Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread
- SMBus-selectable CC/SRIS -0.25% spread
- One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
- Easy AC-coupling to other logic families, see application note AN-891.
- Space saving 5 × 5 mm 40-VFQFPN
Documentation
| Document title | Document type
|
Date Date | |
|---|---|---|---|
| PDF 545 KB | Datasheet | ||
| PDF 91 KB | Application Note | ||
| PDF 1.99 MB | Application Note | ||
| PDF 255 KB | Application Note | ||
| PDF 480 KB | Application Note | ||
| PDF 235 KB | Application Note | ||
| PDF 1.90 MB | Application Note | ||
| PDF 495 KB | Application Note | ||
| PDF 442 KB | Application Note | ||
| PDF 233 KB | Application Note | ||
| PDF 160 KB | Application Note | ||
| PDF 120 KB | Application Note | ||
| PDF 565 KB | Application Note | ||
| PDF 136 KB | Application Note | ||
| PDF 483 KB | Datasheet | ||
| PDF 938 KB | End Of Life Notice | ||
| PDF 909 KB | End Of Life Notice | ||
| PDF 321 KB 简体中文 | Guide | ||
| PDF 838 KB | Manual - Hardware | ||
| PDF 2.40 MB | Overview | ||
| PDF 1.83 MB | Overview | ||
| PDF 171 KB | Product Advisory | ||
| PDF 734 KB | Product Change Notice | ||
| PDF 120 KB | Product Change Notice | ||
| PDF 728 KB | Product Change Notice | ||
| PDF 725 KB | Product Change Notice | ||
| PDF 116 KB | Product Change Notice | ||
| PDF 127 KB | Product Change Notice | ||
| PDF 983 KB | Product Change Notice | ||
| PDF 23 KB | Product Change Notice | ||
| PDF 517 KB | Report | ||
| PDF 33 KB | Schematic | ||
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Design & Development
Software & Tools
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
Processing table
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Output Impedance |
Carrier Type |
Buy / Sample |
|
|---|---|---|---|---|---|---|
| Part Number | ||||||
| VFQFPN | 40 | I | 100 | Tray | Get Samples, | |
| VFQFPN | 40 | I | 100 | Reel | ||
| VFQFPN | 40 | I | 85 | Tray | Get Samples, | |
| VFQFPN | 40 | I | 85 | Reel |
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play_circle_filledVideos & Training
PCIe Reference Clock Jitter Budgets
IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Video List
