Clocks & Timing

Overview

The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen1–5 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRNS) and Separate Reference Independent Spread (SRIS) clocking architectures.
 
For information regarding evaluation boards and material, please contact your local sales representative.
 
9FGL02-04-06-08 - Block Diagram
9FGL0641_51 - Pinout
9FGL02-04-06-08 - Block Diagram
9FGL0641_51 - Pinout
  • PCIe Gen1–5 CC-compliant
  • Supports PCIe SRIS and SRNS clocking
  • Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
  • Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread
  • SMBus-selectable CC/SRIS -0.25% spread
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
  • Easy AC-coupling to other logic families, see application note AN-891.
  • Space saving 5 × 5 mm 40-VFQFPN

Documentation

Title Type Date
9FGL02x1-04x1-06x1-08x1D Family Datasheet
PDF545 KB
Datasheet
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
Application Note
AN-975 Cascading PLLs
PDF255 KB
Application Note
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs
PDF480 KB
Application Note
AN-879 Low-Power HCSL vs Traditional HCSL
PDF235 KB
Application Note
AN-843 PCI Express Reference Clock Requirements
PDF1.90 MB
Application Note
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
Application Note
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
Application Note
AN-839 RMS Phase Jitter
PDF233 KB
Application Note
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
Application Note
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
Application Note
AN-815 Understanding Jitter Units
PDF565 KB
Application Note
AN-802 Crystal-Measuring Oscillator Negative Resistance
PDF136 KB
Application Note
AN-805 Recommended Ferrite Beads
PDF121 KB
Application Note
9FGL02x1-04x1-06x1-08x1 Family Datasheet
PDF482 KB
Datasheet
PLC# : 220001-R1 End-of-Life (EOL) Process on Select Part Numbers
PDF938 KB
End Of Life Notice
PLC# : 220001 End-of-Life (EOL) Process on Select Part Numbers
PDF909 KB
End Of Life Notice
Timing Products for NXP (Freescale) i.MX
PDF321 KB 简体中文
Guide
9FGx08 PCIe Clock Generator Evaluation Boards User Guide
PDF838 KB
Manual - Hardware
PCI Express Timing Solutions Overview
PDF2.40 MB
Overview
IDT Clock Generation Overview
PDF1.83 MB
Overview
PCN# : 220011 (R1) New Revision for 9FGL/9DBL Family
PDF120 KB
Product Change Notice
PCN# : 220011 New Revision for 9FGL/9DBL Family
PDF119 KB
Product Change Notice
PCN# : 220015 Add Alternate Assembly Location on VFQFPN Packages
PDF728 KB
Product Change Notice
PCN# : A2005-01(R1) Add UTL, Thailand and JCET, China as Alternate Assembly Locations
PDF725 KB
Product Change Notice
PCN# : A2005-01 Add UTL, Thailand and JCET, China as Alternate Assembly Locations
PDF116 KB
Product Change Notice
PCN# : TP1910-02 Metal Change to Enhance Spread Performance
PDF127 KB
Product Change Notice
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility
PDF983 KB
Product Change Notice
PCN# : MM1610-01 Improve performance to meet the new PCIe
PDF23 KB
Product Change Notice
9FGL06 Evaluation Board Schematic
PDF33 KB
Schematic
info: For device-specific or order-specific documentation, submit a support request.

Design & Development

Software Downloads

Title Type Date
PLC# : 220001-R1 End-of-Life (EOL) Process on Select Part Numbers
PDF938 KB
End Of Life Notice
PLC# : 220001 End-of-Life (EOL) Process on Select Part Numbers
PDF909 KB
End Of Life Notice
Software for PCIe Evaluation Kits
ZIP440 KB
Software & Tools - Evaluation Software

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PCIe Reference Clock Jitter Budgets

IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

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IDT Adds 3.3 V PCIe Clock Generators to World’s Lowest Power PCI Express Timing Family News