Etienne Winkelmuller
Timing Product Marketing Manager
Published: February 7, 2019

Infotainment and dashboard systems commonly require several clocks: processor clocks, PCI Express clocks, USB clocks, etc. – each characterized by a specific frequency. Out of all the clocks required for infotainment and dashboard applications, the LCD panel dot clocks are probably the most difficult to achieve. Target dot clock frequencies are dictated by an LCD panels’ construction parameters, such as resolution, refresh rate, active/inactive pixels ratio, and so on. Although standard dot clock frequencies exist (such as 27 MHz or 148.5 MHz), some LCD panels require non-standard frequencies. Let’s take two random values as examples, 30.123 MHz and 40.456 MHz.

Traditionally, crystal oscillators (XO) were used to generate each clock within a system. But some frequencies, such as our 30.123 MHz and 40.456 MHz examples, might be difficult or expensive to source.

Today’s designs can rely on integrated, programmable clock generators such as the automotive-grade VersaClock® 6E 5P49V60 to address this issue. The 5P49V60 generates up to 5 different frequencies up to 350 MHz. Thanks to Fractional Output Divider (FOD) PLL technology, the device is suitable to generate the 30.123 MHz and 40.456 MHz of our example.

Let’s take a step back and explore PLL (Phase Locked Loops) technology in more details. A PLL consists of a phase comparator, a low pass filter, a Voltage Controlled Oscillator (VCO) as well as a feedback divider M and (in the case of the VersaClock 6E) four output dividers N1, N2, N3 and N4. The PLL adjusts the VCO frequency so both inputs of the phase comparator “see” the same frequency. If a signal coming from the crystal at, say, 25 MHz, is connected to one input of the phase comparator and the output of the VCO, divided by a factor M=100, is connected to the other input of the phase comparator, the PLL will adjust itself for a VCO frequency of fVCO = 2500 MHz. Suitable VCO frequencies for the VersaClock 6E are in the range of 2500 MHz to 2700 MHz.

PLL Architecture

Dividers of traditional PLLs can only have integer values. Generating our example frequencies of 30.123 and 40.456 MHz can be done in the following ways: (note that other possibilities do exist)

fVCO N1 f1 N2 f2
2590.578 MHz 86 30.123 MHz
(0 ppm error)
64 40.4778 MHz
(>5% error)
2589.184 MHz 86 30.107 MHz
(>5% error)
64 40.456 MHz
(0 ppm error)

As we see, generating output frequencies with a low enough error can prove difficult. Besides, we only considered the limitations of integer output dividers. A similar limitation exists on the feedback divider M if we want to adjust the VCO frequency with respect to available crystal frequencies.

Fortunately, fractional output divider technology has evolved in recent years to the point that having “any” N1, N2, N3, N4 and M ratios (within a specified design range) becomes possible. Generating our LCD dot clock frequencies of 30.123 and 40.456 MHz is easily done by setting N1 and N2 to:

fVCO N1 f1 N2 f2
2500 MHz 82.9931… 30.123 MHz
(0 ppm error)
61.7955… 40.456 MHz
(0.5 ppb error)

This assumes a VCO frequency of 2500 MHz. In this particular case, the 5P49V60 will have 0 ppm error on f1 and 0.5 ppb error on f2. (0.5 ppb is way below the tolerance of a crystal resonator!) Sometimes, the VCO frequency may influence the performance of the part. Finding the best configuration of the VersaClock 6E can be done with Renesas' Timing Commander software. Renesas' Field Application Engineer as well as Application Engineer Teams help fine-tuning the device’s configuration for the best performance.

Visit for more information on the 5P49V60 VersaClock 6E for automotive applications, including documentation and samples. Visit to learn more about Renesas' timing solutions for automotive applications.

In the second part of this series, I’ll address how programmable timing devices can help reduce both development time and qualification costs for automotive systems.

Share this news on

Share this news on