Advantages of the SOTB Process

Extreme low power operation and low leakage current

SOTB realizes approximately 1/10th the power consumption of conventional low-power MCU devices, enabling battery-free products through energy harvesting, or enabling products with extremely long battery life requiring less maintenance – all without sacrificing performance.

SOTB’s combination of dopantless SOI channel, buried oxide insulation layer, and the back-side gate are used to realize the effect shown here. Compared to standard bulk CMOS technology (red), SOTB reduces the voltage threshold variance (blue) for lower operation voltage, lower operation current. With a negative back bias voltage applied to the substrate (green), a SOTB device can almost completely eliminating leakage current during standby.

Graphs of SOTB's extreme low power operation and low leakage current


SOTB enables low, mid, and high-end MCU devices to scale in performance while maintaining superior low power characteristics when compared to MCUs not using SOTB. Shown here, 65nm SOTB is extremely favorable in performance-per-power-consumption compared to non-SOTB processes ranging from 40nm to 180nm.

SOTB: one process, one geometry node size, for a wide product range.

SOTB's scalability

High performance analog and low noise

The dopantless SOI channel of the SOTB process provides high performance analog with low noise, and more accuracy while consuming less power. Shown here are measures of analog accuracy, noise performance, and power consumption of Analog-to-Digital Converters (ADC) on MCU devices with and without SOTB. Both 12-bit and 14-bit ADCs are plotted. The 14-bit Renesas ADC, based on SOTB, is most favorable in high accuracy, low noise, and low power consumption.

Graph of SOTB's high performance analog and low noise

High immunity to data corruption

SOTB’s buried oxide (BOX) insulation layer serves to reduce the impact of particle radiation. The result is a large reduction Soft Error Rate (SER), approaching zero. Shown here are relative SER rates of SOTB and conventional bulk CMOS transistor structures. A soft error is when there is an undesired inversion of logic level of data that is stored in memory or logic circuits. This type of error can corrupt data and/or cause erroneous execution of program code.

SOTB's soft error rate (SER) approaches zero

References: K. Kobayashi et al., IEEE Transactions on Nuclear Science, vol. 61, no. 4, pp. 1881-1888, Aug. 2014.