The V850E/Dx3 is supported only for the customers who have already adopted any of the products.

For new adoption, please contact your regional representative.


Key Features:

  • V850E1 CPU Core
  • Number of instructions 81
  • Minimum instruction execution time
    • 15.625 ns (64 MHz) (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427)
    • 31.25 ns (32 MHz) ( µPD70F3421, µPD70F3422, µPD70F3423)
    • 41.27 ns (24 MHz) (µPD703416, µPD70F3416, µPD703417, µPD70F3417)


  • General registers 32 registers (32 bits each)
  • Instruction set
    • V850E (compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed)
    • Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): 1 to 2 clocks
    • Saturated operation instructions (with overflow/underflow detection)
    • 32-bit shift instructions: 1 clock
    • Bit manipulation instructions
    • Load/store instructions with long/short format
    • Signed load instructions


  • Internal flash memory 128 KB to 2048 KB
  • Internal mask ROM memory 128 KB - 256 KB (µPD703416, µPD703417)
  • Internal data RAM 6 KB to 84 KB
  • Clock Generator
    • Internal spread-spectrum PLL (SSCG) 12-fold/16-fold, up to 64 MHz ± 5 %( µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427) 16 MHz ± 5 % (µPD703416, µPD70F3416, µPD703417, µPD70F3417)
    • Internal PLL 8-fold
    • CPU frequency range: 64 MHz (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427), 32 MHz (µPD70F3421, µPD70F3422, µPD70F3423), 24 MHz (µPD703416, µPD70F3416, µPD703417, µPD70F3417)
    • Peripheral frequency range up to 16 MHz
    • Main crystal frequency range (main oscillator) 4 MHz
    • Sub oscillator 32 KHz (typ.)
    • Internal oscillator 240 KHz (typ.)
    • Clock supervision 2 channels: main oscillator monitor, sub oscillator monitor


  • Auxiliary frequency output
  • Built-in power saving modes


  • External memory bus interface (µPD70F3427 only)
    • Address/data separated busses 24/32-bit
    • Chip select signals 4


  • DMA 4 channels
  • I/O ports
    • Input/output ports : 72 to 101
    • Input ports: 8 to 16


  • A/D Converter :
    • Number of channels: 8 to16 channels
    • Resolution 10-bit
    • Conversion modes : Continuous select mode/Continuous scan mode/Timer trigger mode/Software trigger mode
    • Analog input channels shared with digital input port functionality


  • Serial interfaces:
    • Synchronous: CSI (CSIB): 2 to 3
    • Asynchronous: UART (UARTA) 2 channels with LIN support
    • I2C (IIC): 1 to 2 channels
    • CAN : 1 to 3 channels


  • Timers:
    • 16-bit multi purpose timer/event counter (TMP) 1 to 4 channels
    • 16-bit multi purpose timer/counter (TMG) 2 to 3 channels
    • 16-bit multi purpose timer/counter (TMZ) 6 to 10 channels
    • 16-bit PWM/PFM timer (TMY) 1 channel
    • Watch Timer (WT) 1 channel
    • Watch Calibration Timer (WCT) 1 channel
    • Watchdog Timer (WDT) 1 channel


  • LCD Controller/Driver (µPD70F3421, µPD70F3422, µPD70F3423)
    • Segment signal output max. 40
    • Common signal output max. 4
    • Modes 1/4 duty, 1/3 bias


  • LCD Bus Interface (µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427)
    • Bus width 8-bit parallel
    • Bus control modes 2 modes:
    • RD strobe and WR strobe ("mod80")
    • RD/WR signal and data strobe ("mod68")
    • Transfer speed 100 KHz to 3.2 MHz


  • Stepper Motor Controller/Driver :
    • Number of channels 6 (µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427), 4 (µPD703416, µPD70F3416, µPD703417, µPD70F3417)
    • Resolution 8-bit and 8-bit + 1


  • Sound Generator
    • Number of channels 1
    • Volume 9-bit volume level accuracy
    • Sound frequency 245 Hz to 6 KHz with min. resolution of ± 20 Hz
    • Sound duration 256 steps


  • Interrupts and exceptions
  • Non-maskable interrupts 2 sources
  • Maskable interrupts: 51 to 92 sources
  • Software exceptions: 32 sources
  • Exception trap: 2 sources
  • ROM Correction
  • On-chip debug interface (µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A,
  • µPD70F3427)
    • Number of interfaces 1
    • Connection of an external N-Wire emulator


  • Internal Voltage Comparators
    • Number of channels 2


  • Power supply supervision
  • Power-On-Clear Generates reset at power-up and in case of power loss
  • Single supply operating voltage
    • Range 4.0 V to 5.5 V (µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427) , 3.5 V to 5.5 V (refer to Electrical Target Specification) (µPD703416, µPD70F3416, µPD703417, µPD70F3417)


  • Temperature range: Ta = -40 to +85℃
  • Package : 208-pin QFP (µPD70F3427), 144-pin QFP(µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424,
  • µPD70F3425, µPD70F3426A), 100-pin LQFP (µPD703416, µPD70F3416, µPD703417, µPD70F3417)
  • Package size : 28 mm x 28 mm (µPD70F3427), 20 mm x 20 mm(µPD70F3421, µPD70F3422, µPD70F3423,
  • µPD70F3424, µPD70F3425, µPD70F3426A), 14 mm x 14 mm(µPD703416, µPD70F3416, µPD703417, µPD70F3417)
  • Pin pitch 0.5 mm
  • CMOS technology

Pin Count / Memory Size Lineup:

Program Flash


Below you will find information to support the development of your application.
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Resources for Software and Hardware

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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