概要
説明
The CD4029BMS consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY-OUT OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN-IN and PRE-SET ENABLE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD4029BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X, Frit Seal DIP H1F and Ceramic Flatpack H6W.
特長
- High-voltage type (20V rating)
- Medium-speed operation: 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V
- Multi-package parallel clocking for synchronous high-speed output response or ripple clocking for slow clock input rise and fall times
- "Preset Enable" and individual "Jam" inputs provided
- Binary or decade up/down counting
- BCD outputs in decade mode
- 100% tested for maximum quiescent current at 20V
- 5V, 10V and 15V parametric ratings
- Standardized symmetrical output characteristics
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
- Noise margin (over full package temperature range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
- Meets all requirements of JEDEC tentative standards No. 13B, "Standard Specifications for Description of "B" Series CMOS Device's
アプリケーション
アプリケーション
- Programmable binary and decade counting/frequency synthesizers-BCD output
- Analog-to-digital and digital-to-analog conversion
- Up/Down binary counting
- Difference counting
- Magnitude and sign generation
- Up/Down decade counting
ドキュメント
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| PDF 431 KB | データシート | |
| PDF 467 KB | カタログ | |
| PDF 4.85 MB | カタログ | |
| PDF 360 KB | Price Increase Notice | |
| その他資料 | ||
| PDF 533 KB | ホワイトペーパー | |
| PDF 499 KB | Product Advisory | |
| PDF 230 KB | 製品変更通知 | |
| PDF 338 KB | アプリケーションノート | |
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設計・開発
モデル
ECADモデル
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Processing table
| SBDIP | Tube | 25 | 5962R9562101VEC | ||
| 100 | 5962R9562102V9A | ||||
| 100 | 5962R9562101V9A | ||||
| CFP | Tray | 25 | 5962R9562101VXC |
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