メモリ&ロジック

概要

The IMX3112 is a dual bidirectional 1:2 translating multiplexer for I3C/I²C bus. The input HSDA/HSCL pair can fan out to two output pairs (or channels), either individual output channel can be selected.

Applications with slave devices that share the same address can use this multiplexer to prevent slave address conflicts. By selecting the proper output channel, the I3C/I²C master can access a large number of devices across both ports.

IMX3112 - Block Diagram
IMX3112 - Block Diagram
  • 1:2 bus multiplexer
  • Two-wire programmable I²C or I3C bus serial interface
  • Single device load on the Host bus
  • Up to 12.5MHz transfer rate
  • Single 1.8V power supply input
  • 1.0V VLDO output at VIO pin
  • Supports 1.0V, 1.1V, and 1.2V Push-Pull IO levels
  • Supports 1.0V, 1.1V, 1.2V, 1.8V, 2.5V, and 3.3V open-drain IO levels
  • Integrated Temperature Sensor; 0.5°C accuracy with 0.25°C resolution
  • Packet Error Check (PEC) function
  • Parity Error Check function
  • Bus reset function
  • In-band Interrupt (IBI)
  • Up to 8 unique addresses
  • Programmable I²C, I3C bus addressing scheme
  • 9-contact thermally enhanced DFN package
  • Temperature: Industrial range of -40°C to 85°C

ドキュメント

タイトル 分類 日付
IMX3112 Short-Form Datasheet
PDF41 KB
データシート－簡略版
Memory Multiplexer Family Overview
PDF807 KB
概要

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製品選択

    Processing table
    型名
    Pkg. Type
    Carrier Type
    MOQ
    ご購入 / サンプル
    IMX3112-Y2B000NCG8
    play_circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 DFN Reel 2500
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