特長
- Six low skew, low additive jitter LVDS output pairs
- One differential clock input pair
- Differential PCLK, nPCLK pair can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 1.2GHz (maximum), design target
- Output skew: 20ps (typical)
- Propagation delay: 290ps (typical)
- Low additive phase jitter, RMS
- fREF = 156.25MHz, VPP = 1V, 12kHz to 20MHz: 39fs (typical)
- Full 1.8V supply voltage
- Lead-free (RoHS 6), 20-VFQFPN packaging
- -40 °C to 85 °C ambient operating temperature
説明
The 8P34S1106 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase noise clock and data signals. The 8P34S1106 is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1106 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and six low skew outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the differential device input. The device is optimized for low power consumption and low additive phase jitter.
パラメータ
| 属性 | 値 |
|---|---|
| Outputs (#) | 6 |
| Inputs (#) | 1 |
| Channels (#) | 1 |
| Input Freq (MHz) | - |
| Output Freq Range (MHz) | - |
| Output Skew (ps) | 20 |
| Adjustable Phase | No |
| Noise Floor (dBc/Hz) | -162 |
| Additive Phase Jitter Typ RMS (fs) | 39 |
| Output Type | LVDS |
| Supply Voltage (V) | - |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 4.0 x 4.0 x 1.0 | 20 | 0.5 |