ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
検索

8SLVP1212I

アクティブ
長期製品供給対象

2:12,3.3V,2.5V LVPECL Fanout Buffer

ご購入

特長

  • Twelve low skew, low additive jitter LVPECL outputs
  • Two selectable, differential clock inputs
  • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 2GHz
  • LVCMOS interface levels for the control input (input select)
  • Output skew: 15ps (typical)
  • Propagation delay: 550ps (maximum)
  • Low additive phase jitter, RMS: <50fs (typical)
  • Full 3.3V and 2.5V supply voltage
  • Device current consumption (IEE): 118mA (typical)
  • Available in Lead-free (RoHS 6), 40-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature
RFバッファ内の他の製品を探す
8SLVP1212I - Block Diagram
8SLVP1212I - Pinout
8SLVP1212I - Block Diagram
8SLVP1212I - Pinout

説明

The 8SLVP1212I is a high-performance, 12 output differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1212I is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1212I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

パラメータ

属性 値
Outputs (#) 12
Inputs (#) 2
Channels (#) 1
Input Freq (MHz) -
Output Freq Range (MHz) -
Output Skew (ps) 15
Adjustable Phase No
Noise Floor (dBc/Hz) -160
Additive Phase Jitter Typ RMS (fs) 45
Output Type LVPECL
Supply Voltage (V) - , -

パッケージオプション

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 6.0 x 6.0 x 0.9 40 0.5

適用されたフィルター

読込中
読込中

Description

Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit Renesas's RF Buffer page.

 

Transcript

Hello. My name is Baljit Chandhoke and I'm the product marketing manager of clocking products at IDT. Today, I'll be giving you a brief overview of high performance differential clock fanout buffer family IDT 8SLVP family of LVPECL Buffers and IDT 8SLVD family of LVDS Buffers.
 
Clocks are the basic building blocks for all electronics today. Clock buffers are useful building block of clock trees because they're used to create multiple copies of the input clocks. Since clocks are used to drive processors and to synchronize the transfer of data between system components, the clock distribution system is an essential part of the system design. Hence, identifying the correct clock buffer for a system is extremely important. The key benefits of clock buffers are extreme low additive phase noise to drive jitter sensitive devices. Reduction in board space with reduced bill of material. 
 
Key application of clock buffers: networking, computing, base stations, high end consumer, industrial communications, and instrumentation. Application issues solved by clock buffers: clock fanout to reduce bulk bill of material and board space. Fanout buffers enable frequency synchronized clock outputs to the same clock input reference. Fanout buffers enable low output to output skew between clock outputs. Low propagation delay between input and output clock. Low additive clock jitter at the output clock. 
 
Now I'll talk about the 8SLVP family of LVPECL clock fanout buffers. These are high performance differential LVPECL clock fanout buffers with best in class extremely low additive phase-jitter. They are characterized to operate with a power supply of 3.3 volts and 2.5 volts. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP family ideal for clock distribution applications demanding to modeling well-defined performance and repeatability.
 
The features of 8SLVP family of LVPECL fanout buffers are two selectable differential clock inputs which can accept LVPECL, LVDS or CML inputs. Output skew of 28ps. Propagation delay, 410ps.  Low additive phase jitter with a RMS phase jitter of 54.1fs maximum. The device operates with a 3.3 volt and 2.5 volt power supply and operating temperature range of minus 40 degrees Celsius to 85 degrees Celsius.
 
IDT8SLVP family of LVPECL buffers is offered in different output configurations, with one to two fanouts to one to 12 fanouts. Dual channel options are available with dual one to four fanouts, dual one to eight fanouts. All these devices can operate with an input frequency up to 2 GHz with extremely low additive phase jitter of 50 to 100 fs RMS max. This device family has extremely fast output rise and fall time, with less than 150ps. 
 
Now I'm going to talk about the 8SLVD family of LVDS fanout buffers. This family has optimized for low power consumption small output to output skew and propagation delay and best in class very low additive phase jitter. The key features of this family are two selectable clock inputs which can accept LVPECL or LVDS inputs. Maximum input clock frequency up to 2 GHz. Output skew 20ps max. Propagation delay 300ps. Low additive phase jitter, 95fs. This device family operates with a 2.5 volt supply voltage with some devices being offered with 3.3 volt power supply as well. 
 
This slide shows you the family of devices. We offer LVDS fanout buffers with one to two fanout, dual channel one to two, one to four fanout. Dual channel one to four all the way up to one to 12 fanout buffers, with extremely low additive phase jitter, between 50 and 100fs. 
 
In summary 8SLVP and 8SLVD family is a high performance differential LVPECL and LVDS fanout buffer family from IDT with best in class low additive clock jitter with 50 to 100fs RMS max. Low power consumption, small propagation delay, low output to output skew, fast rise time and fall time. IDT offers an extensive portfolio of single channel and dual channel LVPECL and LVDS fanout buffers from two outputs to 12 outputs.
 
We provide a complete product support with datasheets, timing solutions book, fanout buffer flyers on IDT website. In addition to the 8SLVP and 8SLVD family of fanout buffers we have the largest portfolio of fanout buffers with over 400 devices. IDT is committed to helping our customers with schematic reviews, IBIS or HSpice Models, well-established networks of FAEs in all geographies. Application notes on topics, layout guidelines, crystal selections, power supply filtering. For more information you can contact the link shown. Thank you for your time.

 

読込中 読込中