特長
- 1 - Pair of differential CPU clocks @ 3.3V (CK408)/ 1 - Pair of differential open drain CPU clocks (K7)
- 1 - Pair of differential push pull CPU_CS clocks @ 2.5V
- 3 - AGP @ 3.3V
- 7 - PCI @ 3.3V
- 1 - 48MHz @ 3.3V fixed
- 1 - 24_48MHz @ 3.3V
- 2 - REF @ 3.3V, 14.318MHz
- CPU_CS - CPUT/C: <±250ps
- CPU_CS - AGP: <±250ps
- CPU - DDR: <±250ps
- PCI - PCI: <500ps
- CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
- Programmable output frequency.
- Programmable output divider ratios.
- Programmable output rise/fall time.
- Programmable output skew.
- Programmable spread percentage for EMI control.
- DDR output buffer supports up to 200MHz.
- Watchdog timer technology to reset system if system malfunctions.
- Programmable watch dog safe frequency.
- Support I2C Index read/write and block read/write operations.
- Uses external 14.318MHz crystal.
説明
The 950910 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with PC133 or DDR memory. The 950910 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.