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Low Skew,1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL Fanout Buffer

パッケージ情報

CADモデル: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG20
Lead Count (#): 20
Pkg. Dimensions (mm): 6.5 x 4.4 x 1.0
Pitch (mm): 0.65

環境及び輸出分類情報

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

製品スペック

Lead Count (#) 20
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 0
Qty. per Carrier (#) 74
Package Area (mm²) 28.6
Pitch (mm) 0.65
Pkg. Dimensions (mm) 6.5 x 4.4 x 1.0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) 0 to 70°C
Country of Assembly TAIWAN
Country of Wafer Fabrication SINGAPORE
Additive Phase Jitter Typ RMS (fs) 90
Additive Phase Jitter Typ RMS (ps) 0.09
Core Voltage (V) 3.3
Function Buffer, Multiplexer
Input Freq (MHz) 266
Input Type LVCMOS
Inputs (#) 2
Length (mm) 6.5
MOQ 222
Output Banks (#) 1
Output Freq Range (MHz) 266
Output Skew (ps) 30
Output Type LVPECL
Output Voltage (V) 3.3
Outputs (#) 4
Pkg. Type TSSOP
Price (USD) $2.461
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Thickness (mm) 1
Width (mm) 4.4
掲載 No

説明

The 8535-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 8535-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8535-01 ideal for those applications demanding well defined performance and repeatability.