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UPC811

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Bipolar Single Operational Amplifier, J-FET Input, Low-Offset Voltage, High-Stability for Consumer Products

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Overview

µPC811 is a unique J-FET input operational amplifier that uses a high-speed PNP transistor (fT = 300 MHz)for the output stage to achieve fast response and high stability. The resistor-trimming method proven in other Renesas High-Precision Op-Amp and High-Precision reference voltage is incorporate in this Op-Amp input stage, thus producing an excellent low offset voltage characteristics that has surpasses conventional general purpose op-amp in spite of being JFET input. Along with this series of lineup, the dual type operational amplifier, μPC812 and 4092 with the same circuit configuration are also available.

  • Input Offset Voltage: ±1 mV (TYP.) (±2.5 mV MAX.)
  • VIO Temperature Drift: ±7 µV/°C (TYP.)
  • Input Bias Current: 50 pA (TYP.)
  • Slew Rate: 15 V/µs (TYP.)
  • Unity Gain Frequency: 4 MHz (TYP.)
  • Input Equivalent Noise Voltage Density: 19 nV√ Hz (TYP.) (f = 1 kHz)
  • Stable operation against capacitive load: (Capacitive Load at 10000 pF, AV = +1 )
  • Built-In Phase Compensation Circuit
  • Built-In Output Short Circuit Protection
  • Standard Single Op-Amp terminal connection (pin compatible)

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Models
Type Title Date
Model - SPICE
UPC811 Spice Model
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FAQs

  1. What is offset voltage adjustment via OFFSET NULL pin?

    Adjustment is executed in the input stage's differential amplifier circuits to balance any unbalance (caused by a difference in VBE). Some operational amplifiers have an adjustment pin called the OFFSET NULL pin (see the diagram of the uPC811 below). The offset voltage is adjusted by externally attaching a variable ...

    Mar 1, 2006