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RZ/T1-M

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Equipped with a management data input / output interface (MDIO). Ideal for applications such as optical modules

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Overview

The RZ/T1-M group has the Arm® Cortex®-R4 Processor with FPU designed for real-time processing, capable of high-speed operation at up to 450 MHz. And by equipped with the MDIO interface, The RZ/T1-M group is ideal for applications such as optical modules. 6 x 6mm small package contributes to space saving.

RZ/T1-M Block Diagram
RZ/T1-M Block Diagram
  • CPU: Arm® Cortex®-R4 Processor with FPU, 450MHz
  • Management data input / output interface(Slave/Master)
  • Memory: Tightly Coupled Memory 544KB(with ECC), Extended SRAM 1MB(with ECC, option)
  • Analog function: 12-bit A/D Converter Unit0 : 8ch,Unit1 : 8ch
  • Package: 112-pin FBGA
  • Voltage: Core 1.2V, I/O 3.3V

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Diagram of ECAD Models

Models
Type Title Date
Model - IBIS
RZ/T1-M Group 112pin FBGA (PLBG0112KA-A) IBIS Rev.1.0
Log in to Download IBS 859 KB 日本語
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Resources

Support Communities

  1. RZ/T1 MPUs endat info

    Hello to all I saw in the manual RZ/T1 (example R7S910018CBG) that the Endat function is defined as "optional" .... I don't understand ... if I take a "sample" of this MPUs in the Renesas website this function is present or not. If I look for a "sample" MPUs ...

    Nov 13, 2020
  2. Thermal resistance of RZ/T1 Microprocessors

    I can't find the thermal resistances for calculating junction temperature on the RZ/T1 processors. Can someone please help me with this information? or any alternate ways  Thanks [locked by: Michael Quirk at 19:47 (GMT 0) on 24 Jul 2024]

    Jul 24, 2024
  3. RZ/T1 MCU -peripheral sharing issue

    Hello. We plan to be new designers of the RZ/T1 MCU. we need to connect a FPGA to the MCU for deterministic serial data streams (target is 200Mbps) . Can we use the SPIBSC for that (shared with the S-Flash) ? can we use the RSPIa as quad SPI ...

    Apr 20, 2020
View All Results from Support Communities (9)

FAQs

  1. RZ/T1 : Memory barrier instructions

    Cortex-R4 supports the following three memory barrier instructions. DMBMemory access instructions after DMB instruction are not executed until all memory accesses before DMB instruction are completed.However, instructions except memory access are executed.Execute DMB instruction when expecting that all memory accesses before DMB instruction will be completed. DSBInstructions ...

    Mar 31, 2021
  2. RZ/T1: Missing Parameters for the Loader in External Flash

    The errors "Checksum error of the parameters for the loader" or "Error in a parameter for the loader" will occur and the CPU will go into a infinite loop during boot processing.  Also, the error information is stored in the dedicated address of "0080 09C4h". For more details, refer to ...

    Sep 27, 2017
  3. RZ/T1 : MSL (Moisture Sensitivity levels)

    MSL of RZ/T1 is 3. For details of MSL, refer to the following URL. https://www.renesas.com/us/en/support/technical-resources/packaging/packing/handling.html

    Mar 5, 2021