Overview
Description
The R8C/L3AM Group is supported only for customers who have already adopted these products. The RL78/L1C Group is recommended for new designs.
The R8C/L35M Group, R8C/L36M Group, R8C/L38M Group, and R8C/L3AM Group of single-chip MCUs incorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency and supports a 1Mb address space, allowing execution of instructions at high speed. In addition, the CPU core integrates a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce the number of system components. These groups have data flash (1KB × 4 blocks) with the background operation (BGO) function.
Comparison
Applications
Design & Development
Support
Support Communities
Resources
FAQs
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SDA fixed low during I2C communication, R8C master
A clock discrepancy may occur between the master and slave due to noise, etc. on the SCL line of the I2C bus. This occurs due to differences in VIH/VIL characteristics or noise elimination capabilities of the two devices causing a difference in whether or not noise, etc. on ...
Sep 30, 2016 -
SDA fixed low, R8C master I2C bus interface
A clock discrepancy may occur between the master and slave due to noise, etc. on the SCL line of the I2C bus. This occurs due to differences in VIH/VIL characteristics or noise elimination capabilities of the two devices causing a difference in whether or not noise, etc. on ...
Oct 6, 2016 -
Block erase time standard and maximum values
As the number of program/erase endurance increases, the block erase time tends to lengthen.
Oct 5, 2016