Overview
Description
The R11F MPEG-4 AVC/H.264 Encoder is a broadcast quality real-time encoder designed for live streaming applications using FPGA acceleration tightly coupled with general purpose CPUs. Leveraging technological expertise from ASIC and CPU designs, the R11F provides the best of both worlds in a scalable OPEX friendly platform for a high density of video transcoding.
Features
- Multiscreen optimized H.264/MPEG-4 AVC Encoder
- IDR aligned multiple resolution outputs for OTT packaging
- Unique Computational Control System for highly efficient content adaptive encoding to maximize video quality
- Seamless integration into existing cloud workflows with FFmpeg framework plug-in support
- Live and File Input/Output
- H.264 profiles: high, main, baseline
- Dynamic GOP structure with up to 7 B frames
- Production ready deployment on public cloud services such as Amazon AWS F1 instance
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 313 KB | |
| Datasheet - Short-Form | PDF 175 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
Support Communities
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RX Instruction DIV: How to get the remainder?
I found no "modulo" division within the RX instruction set. Is there a way getting the remainder after executing the "DIV" instruction?Any hint appreciated
Oct 18, 2011