Name: 9QXL2000C - 20-Output Enhanced DB2000Q PCIe Clock Buffer
Brand: Renesas Electronics Corporation
SKU: 9QXL2000C - 20-Output Enhanced DB2000Q PCIe Clock Buffer
Availability: OutOfStock

Features

Low-Power HCSL (LP-HCSL) 85Ω outputs eliminate 80 resistors, saving 130mm² of area
Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
8 OE# pins configurable to control up to 20 outputs
9 selectable SMBus addresses
Spread spectrum compatible
10mm × 10mm 72-VFQFPN package

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Description

The 9QXL2000C is a 20-output very-low additive phase jitter fanout buffer for PCIe Gen1 through Gen6. It offers integrated terminations for 85Ω transmission lines.

Parameters

Attributes	Value
Diff. Outputs	20
Diff. Output Signaling	LP-HCSL
Output Freq Range (MHz)	1 - 400
Diff. Inputs	1
Diff. Input Signaling	HCSL
Accepts Spread Spec Input	Yes
Power Consumption Typ (mW)	739
Supply Voltage (V)	3.3 - 3.3
Output Type	LP-HCSL
Diff. Termination Resistors	24
Package Area (mm²)	81
Battery Backup	No
Battery Seal	No
CPU Supervisory Function POR	No
Crystal Frequency Trimming	No
Frequency Out Pin	No
Inputs (#)	1
Input Freq (MHz)	1 - 400
Function	Fanout Buffer
Input Type	HCSL
Output Banks (#)	1
Core Voltage (V)	3.3
Output Voltage (V)	0.7

Package Options

Pkg. Type	Pkg. Dimensions (mm)	Lead Count (#)	Pitch (mm)
VFQFPN	10.0 x 10.0 x 1.0	72	0.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.

Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.

The 9ZXL1951D is designed to create clocks for PCI Express Generation 4. This video demonstrates how the reference clock for the 9ZXL1951D does not need to be PCI Express Gen4 compliant. When using the Low Bandwidth mode, the 9ZXL1951D will attenuate jitter so its output clocks still pass PCI Express Gen4, even when the input clock only passes PCI Express Gen3. This is most useful when the clock has spread spectrum modulation because it is very difficult to make a very low noise spreading clock.

Related Resources

A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.

Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.

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9QXL2000C

20-Output Enhanced DB2000Q PCIe Clock Buffer

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