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Programmable Timing Control Hub™ for Next Gen P4™ processor

Package Information

Lead Count (#) 48
Pkg. Type TSSOP
Pkg. Code PAG48
Pitch (mm) 0.5
Pkg. Dimensions (mm) 12.5 x 6.1 x 1.0

Environmental & Export Classifications

Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001
Moisture Sensitivity Level (MSL) 1

Product Attributes

Pkg. Type TSSOP
Lead Count (#) 48
Pb (Lead) Free Yes
Carrier Type Tube
C-C Jitter Max P-P (ps) 125
Chipset Manufacturer VIA
Core Voltage (V) 3.3
Die Form No
Diff. Output Signaling HCSL
Function Clock Generator
Input Freq (MHz) 14.318 - 400
Length (mm) 12.5
MOQ 156
Moisture Sensitivity Level (MSL) 1
Output Freq Range (MHz) 14.318 - 400
Output Voltage (V) 2.5, 3.3
Package Area (mm²) 76.3
Pb Free Category e3 Sn
Pitch (mm) 0.5
Pkg. Dimensions (mm) 12.5 x 6.1 x 1.0
Qty. per Carrier (#) 39
Qty. per Reel (#) 0
Reference Output No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum Yes
Supply Voltage (V) 2.5 - 2.5, 3.3 - 3.3
Tape & Reel No
Temp. Range 0 to 70°C
Thickness (mm) 1
Width (mm) 6.1
Xtal Freq (MHz) 14.3182 - 14.3182
Xtal Inputs (#) 1

Description

The 952926 is a 48-pin clock chip for VIA VX/CX 700 style chipsets. When used with a fanout DDR buffer, such as the 93788, it provides all the necessary clock signals for such a system.
The 952926 is part of a line of IDT clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates the newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.