Package Information
| Lead Count (#) | 20 |
| Pkg. Code | NLG20 |
| Pitch (mm) | 0.5 |
| Pkg. Type | VFQFPN |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 1.0 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 20 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Additive Phase Jitter Typ RMS (ps) | 114 |
| Core Voltage (V) | 3.3 |
| Divider Value | 1, 2, 4, 5, 8 |
| Function | Buffer, Divider |
| Input Freq (MHz) | 0 - 2000 |
| Input Type | LVCMOS, LVPECL, LVDS |
| Inputs (#) | 2 |
| Length (mm) | 4 |
| MOQ | 2500 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 0 - 250, 0 - 400, 0 - 500, 0 - 1000, 0 - 2000 |
| Output Skew (ps) | 22 |
| Output Type | LVDS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 16.0 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 4 |
Resources for 8V74S4622
Description
The 8V74S4622 is a versatile clock fanout buffer/frequency divider. The device supports the selection, division, and distribution of high-frequency clock signals with very low additive phase noise. The 8V74S4622 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection and internal isolation.
Two selectable inputs are supported for differential and single-ended clocks. Each of the two outputs can select a copy or a frequency-divided input signal. The available frequency divisions are divided by 2, 4, 5, and 8. Both outputs support LVDS interfaces. For each of the two outputs, a synchronous output-enabled control is implemented for stopping the output clock synchronously to the input clock signal. All device configurations are through a logic pin interface. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.