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15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL Zero Delay Clock Buffer

Package Information

Lead Count (#) 16
Pkg. Code PGG16
Pitch (mm) 0.65
Pkg. Type TSSOP
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

Product Attributes

Lead Count (#) 16
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 0
Qty. per Carrier (#) 96
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range 0 to 70°C
C-C Jitter Max P-P (ps) 65
C-C Jitter Typ P-P (ps) 50
Core Voltage (V) 3.3, 2.5
Divider Value 4, 8
Input Freq (MHz) 15.625 - 62.5
Input Type LVCMOS
Inputs (#) 1
Length (mm) 5.0
MOQ 96
Output Banks (#) 1
Output Freq Range (MHz) 15.625 - 62.5
Output Signaling LVCMOS
Output Skew (ps) 65
Output Type LVCMOS
Output Voltage (V) 3.3, 2.5
Outputs (#) 3
Package Area (mm²) 22.0
Pitch (mm) 0.65
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Pkg. Type TSSOP
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Thickness (mm) 1.0
Width (mm) 4.4

Description

The 86004 is a high performance 1:4 LVCMOS/LVTTL Clock Buffer. The 86004 has a fully integrated PLL and can be configured as zero delay buffer and has an input and output frequency range of 15.625MHz to 62.5MHz. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider.