Skip to main content
4:4 Differential-to-LVPECL/LVDS Clock Multiplexer

Package Information

Lead Count (#) 24
Pkg. Code PGG24
Pitch (mm) 0.65
Pkg. Type TSSOP
Pkg. Dimensions (mm) 7.8 x 4.4 x 1.0

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

Product Attributes

Lead Count (#) 24
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 0
Qty. per Carrier (#) 62
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range -40 to +85°C
Additive Phase Jitter Typ RMS (fs) 220
Additive Phase Jitter Typ RMS (ps) 0.22
Adjustable Phase No
Advanced Features Universal outputs
Channels (#) 1
Core Voltage (V) 2.5, 3.3
Function Buffer, Multiplexer
Input Freq (MHz) 0 - 3000
Input Type CML, LVDS, LVPECL
Inputs (#) 4
Length (mm) 7.8
MOQ 62
Output Banks (#) 1
Output Freq Range (MHz) 0 - 3000
Output Skew (ps) 25
Output Type LVDS, LVPECL
Output Voltage (V) 2.5, 3.3
Outputs (#) 4
Package Area (mm²) 34.3
Pitch (mm) 0.65
Pkg. Dimensions (mm) 7.8 x 4.4 x 1.0
Pkg. Type TSSOP
Prog. Interface Pin select
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Supply Voltage (V) 2.5 - 2.5, 3.3 - 3.3
Tape & Reel No
Thickness (mm) 1
Width (mm) 4.4

Description

The 859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The outputs for this device can either be programmed to give LVPECL or LVDS levels. The 859S0424I has four selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.