Features
- 8-pin SOIC package - Pb-free, RoHS compliant
- Absolute jitter ±100 ps
- Propagation Delay of ±600 ps
- Output multiplier of 2X
- Output clock frequency up to 80 MHz
- Can recover degraded input clock duty cycle
- Output clock duty cycle of 45/55
- Full CMOS clock swings with 25 mA drive capability at TTL levels
- Advanced, low power CMOS process
- Operating voltage of 3.3 V or 5 V
Description
The 2402 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase-Locked Loop (PLL) techniques. The chip is part of IDT's ClockBlocksTM family and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. The 2402 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.
Support Communities
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RX slow clock on powerup, but fine after reset
I have a project that i am doing using a RX62N. about 80-90% of the time, when I power-up, the processor will be running much slower than expexted. But, if it gets into this slow state, if i do a hard reset, the uC will be running normally ...
Apr 19, 2011 -
GPAK internal Vref accuracy
Hi, Could you please provide an approximate GPAK internal Vref accuracy? For whole Vdd range (or for 1.8V, 3.3V, 5.5V if it varies a lot). Thank you in advance. BR, Yurii
May 23, 2018 -
CUSTS1_VAL_NTF_REQ message duplicated
I've a problem if I send CUSTS1_VAL_NTF_REQ messages too fast. If I send e.g. 3 different messages (e.g. "A", "B" and "C") the SDK is sending 3 to the central, but the central receives often the following messages "B", "B", "C" or "B", "C ...
May 25, 2018
Support Communities
