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RZ/A1M

RZ/A1M is a full-featured part in the RZ/A1 family with an ARM® Cortex®-A9 core running at 400MHz and 5MB of on-chip SRAM to support large frame-buffers on-chip.

 

With 5MB on-chip SRAM, the RZ/A1M supports up to 2 Displays with WSVGA (1024x600) resolution or a single display with WXGA (1280x800) resolution without the need for external memory. RZ/A1M enables very compact embedded designs without the need to worry about memory procurement and memory EOL. With RZ/A1M, you can design your embedded system like an MCU and get the performance of a 400MHz ARM® Cortex®-A9 MPU. Enabled for support with Linux, RTOS or Bare-metal, this is the ideal device for designing Intelligent IoT End Point devices with compactness and high performance. Supported in QFP and BGA packages with different sizes to support board layout flexibility and with SDRAM interface to expand up to 128MB of external memory.

 

 

Product Brochure

RZ/A1 Product Brochure

Key Features:

ITEM RZ/A1M

Part name/use/

package
256
pin
R7S721010VLFP
Car Accessory
256-pinQFP (28mm×28mm)
0.4mm pitch
R7S721010VCFP
Industry usage etc..
256-pinQFP (28mm×28mm)
0.4mm pitch
R7S721010VCBG
Industry usage etc..
256-pinBGA (11mm×11mm)
0.5mm pitch
324
pin
R7S721011VLBG
Car Accessory
324-pinBGA (19mm×19mm)
0.8mm pitch
R7S721011VCBG
Industry usage etc.
256-pinBGA (11mm×11mm)
0.5mm pitch

Power supply voltage

3.3V/1.18V

Maximum operating frequency

400MHz

CPU core

ARM® Cortex®-A9 (with Jazelle and NEON)

On-chip RAM

Large-capacity memory: 5 MB
(For video display/work area; 128 KB are shared with data retention)

Cache memory

Primary cache memory: 64 KB (separated 32K instruction/32K data, TLB128 entry)
Secondary cache memory: 128 KB (with CoreLink™ Level 2 Cache Controller L2C-310)
External memory

Bus clock: up to 66.67 MHz

Direct connection to SRAM, byte select SRAM, SDRAM, and
burst ROM (clock synchronous/clock asynchronous) using bus state controller.
Address/data multiplexer I/O (MPX) interface supported.

Address space: 64 MB × 6

Data bus width: external 8/16/32 bits

Graphics functions

OpenVG1.1 2D graphics accelerator
Video display controller
(2 channels of video input and 2 channels of panel output,
of which 1 channel supports LVDS)
Video decoder × 2 channels (analog composite direct input is possible)
Distortion correction engine × 2 channels (requires nondisclosure agreement)
Distortion correction engine for display (requires nondisclosure agreement)
Display out compare unit
JPEG codec unit
Capture engine unit (CMOS camera interface)
Pixel format converter × 2 channels

Audio functions

SCUX (with built- in asynchronous sampling rate conversion, digital volume & mute, and mixer function)
Serial sound interface × 6 channels
Renesas SPDIF interface
Sound generator × 4 channels
CD-ROM decoder

Timer functions

Multifunction 16-bit timer (MTU2) × 5 channels
32-bit OS timer × 2 channels
Motor control PWM timer × 8 channels
Watchdog timer
Real-time clock

Connectivity functions

USB 2.0 host/function module × 2 channels (host or functon selectable)
NAND flash interface
SD host interface × 2 channels (must obtain SD card license)
MMC host interface
Ethernet controller (10 Mbps/100 Mbps transfer, IEEE802.3 PHY interface MII)
Ethernet AVB (IEEE802.1 Audio/Video Bridging) controller (requires nondisclosure agreement)
SPI multi I/O bus controller × 2 channels
(up to 2 serial flash memory connectable to 1 channel, direct execution from CPU supported)
Serial communication interface with 16-stage FIFO
(SCIF) × 8 channels
(asynchronous and clock synchronous serial communication possible)
Serial communication interface × 2 channels
(smart card interface, IrDA 1.0)
Renesas serial peripheral interface × 5 channels
I2C bus interface × 4 channels
Media Local Bus (MediaLB Ver2.0)
Controller area network (CAN) × 5 channels
Local interconnect network interface
(LIN) × 2 channels

System analog functions

Clock pulse generator (CPG): built-in PLL, maximum 32 times multiplication, built-in SSCG circuit
Direct memory access controller × 16 channels
Interrupt controller (with ARM® Generic Interrupt Controller [PL390])
A/D converter (12- bit resolution) × 8 channels
Debugging interface
CoreSight™ architecture
JTAG standard pin layout

Optional function

Secure Boot Engine (requires nondisclosure agreement)
Boot modes Boot mode 0: Boot from memory connected to CS0 space (16-bit bus)
Boot mode 1:
Boots from memory connected to CS0 space (32-bit bus)
Boot mode 2:
(not defined)
Boot mode 3:
Boot from serial flash memory
Boot mode 4:
Boot from built-in NAND flash memory of SD controller
Boot mode 5:
Boot from built-in NAND flash memory of MMC controller
Power-down modes Sleep mode
Software standby mode
Deep standby mode
Module standby mode

 

Pin count /Memory size Lineup:

SRAM
5120KB
Pins
Package
256
LFQFP
256
LFBGA
324
FBGA

 

Block Diagram:

RZ/A1M Block Diagram

*ARM, Cortex, CoreLink, and CoreSight are registered trademarks or trademarks of ARM Limited.
OpenVG is a trademark of the Khronos Group.
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
LIN (Local Interconnect Network): An automotive network specification established by the LIN Consortium.
MediaLB (Media Local Bus): A registered trademark of SMSC, and an automotive network specification developed by SMSC.
IEBus™ (Inter Equipment Bus) is a trademark of Renesas Electronics Corporation.
All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

 

Resources for Software and Hardware

Title Description
My Renesas Create a My Renesas account to use our tool download services, receive e-newsletter/update notifications, and take advantage of our other services.
e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas products.
Video Watch videos related to this product.

 

Resources for Software and Hardware

Title Description
e2 studio Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project.

 

Hardware Design Support

Title Description
IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

Oscillation circuit characteristics
(KYOCERA)
Search for part name starting with "R7S72101" (part name are listed on each product group page) on the oscillator manufacturer's Web site to check for supported oscillators. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.
Oscillation circuit characteristics
(Murata)
Search for part name starting with "R7S72101" (part name are listed on each product group page) on the oscillator manufacturer's Web site to check for supported oscillators. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.
Circuit CAD data, board CAD data Circuit diagram CAD data and substrate CAD data are offered. Please use it by all means.
You can filter the sample codes and application notes that are displayed using the below filters.

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The information contained herein has been provided by a member of Renesas Partners. This information is provided on the Renesas website provided for convenience and informational purposes only. Renesas is not responsible for the contents of this page or any changes or updates to the information posted on this page. Certain links provided herein permit you to leave this site and enter non-Renesas sites. These linked sites are not under control of Renesas. Renesas is not responsible for the contents of any linked site or any changes or updates to such sites. These links are provided for convenience and informational purposes only. The inclusion of any link does not imply endorsement by Renesas of any linked site.

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