Overview

Description

The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.

Features

  • High-speed access and chip select times – Military: 20/25/35/45/55/70/90/120/150ns (max.) – Industrial: 20/25ns (max.) – Commercial: 15/20/25ns (max.)
  • Low-power consumption
  • Battery backup operation – 2V data retention voltage (LA version only)
  • Produced with advanced CMOS high-performance technology
  • CMOS process virtually eliminates alpha particle soft-error rates
  • Input and output directly TTL-compatible
  • Static operation: no clocks or refresh required
  • Available in ceramic 24-pin DIP, ceramic and plastic 24-pin Thin Dip and 24-pin SOIC packages
  • Military product compliant to MIL-STD-833, Class B

Documentation

Type
Date
PDF 118 KB Datasheet
PDF 471 KB 日本語 Guide
PDF 1.11 MB End Of Life Notice
PDF 1.27 MB 日本語 Guide
PDF 1.29 MB End Of Life Notice
PDF 1.22 MB End Of Life Notice
PDF 1.15 MB End Of Life Notice
PDF 160 KB End Of Life Notice
PDF 611 KB Product Change Notice
PDF 611 KB Product Change Notice
PDF 27 KB Product Change Notice
PDF 24 KB Product Change Notice
12 items

Design & Development

Software & Tools

Software Downloads

Type Date
PDF 1.11 MB End Of Life Notice
PDF 1.29 MB End Of Life Notice
PDF 1.22 MB End Of Life Notice
PDF 1.15 MB End Of Life Notice
PDF 160 KB End Of Life Notice
5 items

Models

Support