Overview

Description

The 72V2113 512K x 9/256K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.

Features

  • Functionally compatible with the 72V255/65/75/85 SuperSync FIFOs
  • Up to 166 MHz Operation of the Clocks
  • User selectable Asynchronous read and/or write ports (BGA Only)
  • User selectable input and output port bus-sizing
  • Pin to Pin compatible to the SuperSync II 72V2x3 devices
  • 5V tolerant inputs
  • Auto power down minimizes standby power consumption
  • Master Reset clears entire FIFO
  • Partial Reset clears data, but retains programmable settings
  • Easily expandable in depth and width
  • JTAG port, provided for Boundary Scan function (BGA Only)
  • Independent Read and Write Clocks
  • Available in a 80-pin TQFP or a 100-pin BGA packages
  • Industrial temperature range (–40C to +85C) is available

Documentation

Document title Document type
Type
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PDF 388 KB Datasheet
PDF 211 KB Application Note
PDF 645 KB End Of Life Notice
PDF 123 KB Guide
PDF 567 KB Product Change Notice
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21 items

Design & Development

Software & Tools

Software Downloads

Software title Software type Type Date Date
PDF 645 KB End Of Life Notice
1 item

Models

Models

Title Type Type Date Date
ZIP 2 KB Model - BSDL
ZIP 37 KB Model - IBIS
TAR 48 KB Model - SPICE
3 items

Support