Renesas synchronous FIFO products are ideal for network, video, telecommunications, local area networks (LANs), data communications and other applications that need to buffer large amounts of data. Synchronous FIFO memories have clocked read and write controls along with two fixed flags (empty and full) and two programmable flags (almost-empty and almost-full). Renesas synchronous FIFO devices are depth expandable using a daisy chain technique.

About Synchronous FIFO Devices

Synchronous FIFOs are a type of data buffer, where the first byte to arrive at the input is the first to leave at the output. In a computer system, the operating system’s algorithm schedules CPU time for each process according to the order in which it is received. A synchronous FIFO will queue the data and release it in a sequential fashion.

Renesas synchronous FIFOs are typically used for synchronization of CPU and other computer hardware. FIFOs are generally implemented as a circular queue, and thus have a read and write pointer. Synchronous FIFOs use clocks for reading and writing, while asynchronous FIFOs are usually controlled by asynchronous signals.

Key parameters for choosing a synchronous FIFO include:

  • Density: This is the number of bits the synchronous FIFO will hold in its register. Renesas offers sizes up to 18Mb.
  • Bus width: The number of “lanes” used to read and write to the device. Renesas offers all popular configurations.
  • Core voltage: The supply voltage used to power the device. This is typically defined by the power rails available in the system.
  • I/O voltage: The voltage used for the data input and output, for some devices this is separate from the core voltage
  • I/O frequency: The supported frequencies for the clocking signals. Renesas synchronous FIFOs support frequencies up to 225MHz.


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Guide PDF 97 KB
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