The 72V51443 multi-queue flow-control device is a single chip within which between 1 and 16 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.


  • Total Available Memory = 1,179,648 bits
  • 166 MHz High speed operation (6ns cycle time)
  • 3.7ns access time
  • Available Memory in blocks of 512 x 18 or 1,024 x 9
  • Independent Read and Write access per queue
  • 100% Bus Utilization, Read and Write on every clock cycle
  • Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width)
  • User Selectable Bus Matching Options: - x18in to x18out - x9in to x18out - x18in to x9out - x9in to x9out
  • FWFT mode of operation on read port
  • JTAG Functionality (Boundary Scan)
  • Available in a 256-pin PBGA package
  • Industrial temperature range (-40C to +85C) is available




Design & Development