The Renesas FIFO multi-queue flow-control device is a fully programmable device, providing the user with flexibility in how queues are configured. The Renesas multi-queue device services conflicting demands by ordering process for the best product performance. Multi-queue FIFOs are a single chip solution with the capability to set up between 1 and 4 discrete FIFO queues. Bus matching is available on queuing FIFOs, where either port can be 9 bits, 18 bits, or 36 bits wide.

Memory & Logic

Product Selection Table

    Processing table
    Part Number
    Core Voltage (V)
    Bus Width (bits)
    Density (Kb)
    Pkg. Code
    Interface
    I/O Type
    I/O Frequency (MHz)
    Organization
    Temp. Range
    Architecture
    105°C Max. Case Temp.
    72V51253
    4Q x18 2M Multi-Queue, 3.3V    		 3.3 18 2048 BB256, BBG256 Synchronous 3.3 V LVTTL 166, 133 32K x 18 x 4, 64K x 9 x 4 0 to 70°C Multi-Queue
    72V51256
    4Q x36 2M Multi-Queue, 3.3V    		 3.3 36 2048 BB256 Synchronous 3.3 V LVTTL 166, 133 16K x 36 x 4 0 to 70°C Multi-Queue
    72V51443
    16Q x18 1M Multi-Queue, 3.3V    		 3.3 18 1024 BB256 Synchronous 3.3 V LVTTL 166, 133 4K x 18 x 16, 8K x 9 x 16 0 to 70°C Multi-Queue
    72V51446
    16Q x36 1M Multi-Queue, 3.3V    		 3.3 36 1024 BB256 Synchronous 3.3 V LVTTL 166, 133 2K x 36 x 16 0 to 70°C Multi-Queue
    72V51456
    16Q x36 2M Multi-Queue, 3.3V    		 3.3 36 2048 BB256 Synchronous 3.3 V LVTTL 166, 133 4K x 36 x 16 0 to 70°C Multi-Queue
    Parametric Table tips

    Tips for Using This Parametric Table:

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    Documentation

    Title Type Date
    IDT FIFO Products Package and Ordering Information
    PDF97 KB
    Guide
    IDT Specialty Memory Products Overview
    PDF890 KB
    Overview
    Best In Class FIFO Products
    PDF1.82 MB
    Overview

    Tools & Resources

    FIFO Product FAQs