The RC32112A regenerates and distributes ultra-low jitter clock outputs and features up to 6 independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 56Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards and wireless small cell applications.


  • Two timing channels and six independent frequency domains
  • Output jitter below 100fs RMS
  • Digital PLLs (DPLLs) lock to any frequency from 0.5kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • Can be used as a jitter attenuator, clock generator, or synchronizer
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory
    • Standard external I2C EPROM via separate I2C Master Port




Type Title Date
Datasheet PDF 2.54 MB
Application Note PDF 704 KB
Application Note PDF 164 KB
Guide PDF 2.93 MB
Overview PDF 320 KB
Application Note PDF 1.92 MB
Application Note PDF 2.13 MB
Guide PDF 10.53 MB
Application Note PDF 1.62 MB
Application Note PDF 354 KB
Application Note PDF 390 KB
Application Note PDF 880 KB
Guide PDF 2.40 MB
Application Note PDF 584 KB
Product Change Notice PDF 301 KB
Application Note PDF 162 KB
Application Note PDF 739 KB
Application Note PDF 633 KB
Product Change Notice PDF 123 KB
Product Change Notice PDF 435 KB
Application Note PDF 479 KB
Application Note PDF 442 KB
Application Note PDF 566 KB
Application Note PDF 976 KB
Application Note PDF 659 KB
Application Note PDF 324 KB
Schematic PDF 206 KB
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Design & Development

Software & Tools

Software Downloads

Type Title Date
Software & Tools - Software GZ 500 KB
Software & Tools - Other ZIP 51.88 MB
Software & Tools - Other ZIP 18.02 MB
Software & Tools - Other ZIP 278 KB
Software & Tools - Other ZIP 73 KB
Software & Tools - Other ZIP 177 KB
Software & Tools - Other ZIP 177 KB
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Type Title Date
Model - IBIS ZIP 2.55 MB
Model - BSDL ZIP 2 KB
Model - BSDL BSDL 12 KB
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IDT ClockMatrix™ Timing Solution for 100Gbps Interface Speeds (IEEE 1588, OTN, and SyncE)

Introducing the IDT ClockMatrix™ family of devices - high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. 

They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

For more information, visit www.idt.com/clockmatrix.