8V19N850 Evaluation Kit
The evaluation kit supports electrical AC and DC measurements of the 8V19N850DNLGI, a fully integrated radio synchronizer and JESD204B/C clock jitter attenuator. The...
The 8V19N850 is a fully integrated Radio Unit Clock Synchronizer and Jitter Attenuator designed as a high-performance clock solution for phase/frequency synchronization and signal conditioning of wireless base station radio equipment. The device supports JESD204B/C subclass 0 and 1 device clocks and SYSREF synchronization for converters. The 8V19N850 supports two independent frequency domains: one that can be used for the digital clock (Ethernet and FEC rates) domain with four outputs, and the device clock (RF-PLL) domain with 12 outputs. The Ethernet domain generates frequencies from two independent APLLs for flexibility; the outputs of the RF clock domain generate very low phase noise clocks for ADC/DAC circuits.
From the integrated RF-PLL, the device supports the clock generation of high-frequency device clocks for driving ADC/DAC devices low-frequency synchronization signals (SYSREF). A dual DPLL front-end architecture supports any frequency translation. Each DPLL provides a programmable bandwidth and a DCO function for real-time frequency/phase adjustments. The DPLLs can lock on 1PPS input signals and establish lock within 100s or less. Frequency information can be applied from DPLL-0 to DPLL-1 and vice versa to enable the combining of the frequency characteristics of two references (combo-mode). The 8V19N850 is configured through a pin-mapped I3C (including legacy I2C) and 3/4-wire SPI interface. I2C with master capabilities reads a default configuration from an external ROM device. GPIO ports can be configured for reporting and controlling purposes.
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Type | Title | Date |
Datasheet | PDF 2.86 MB | |
Product Change Notice | PDF 550 KB | |
Application Note | PDF 164 KB | |
Application Note | PDF 91 KB | |
Application Note | PDF 1.99 MB | |
White Paper | PDF 400 KB | |
Manual - Development Tools | PDF 2.66 MB | |
Application Note | PDF 261 KB | |
Guide | PDF 401 KB | |
Report | PDF 2.55 MB | |
Application Note | PDF 41 KB | |
Overview | PDF 331 KB | |
Application Note | PDF 495 KB | |
Application Note | PDF 115 KB | |
Application Note | PDF 233 KB | |
Application Note | PDF 565 KB | |
Application Note | PDF 438 KB | |
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The evaluation kit supports electrical AC and DC measurements of the 8V19N850DNLGI, a fully integrated radio synchronizer and JESD204B/C clock jitter attenuator. The...
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Select an orderable part number:
Orderable Part ID | Sample |
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8V19N850DNLGI | Availability |
8V19N850DNLGI/W | Availability |
8V19N850DNLGI8 | Availability |
This video introduces the industry’s first fully-integrated synchronizer for 5G enhanced common public radio interface (eCPRI) radio synchronization.
Selecting the Best Device for Converter Clocking Applications | Blog Post | Feb 1, 2022 |