The 8V19N491-24 is a fully integrated FemtoClock NG Jitter Attenuator and Clock Synthesizer that is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, LTE-A and 5G radio board implementations.
The device supports JESD204B/C subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.
The 8V19N491-24 supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through a selectable 3/4-wire SPI interface and reports lock and signal loss status in internal registers and via an lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The 8V19N491-24 is ideal for driving converter circuits in wireless infrastructure, radar/imaging and instrumentation/medical applications.
For information regarding evaluation boards and material, please contact your local IDT sales representative.
- High-performance clock RF-PLL with support for JESD204B/C
- Optimized for low phase noise: -153dBc/Hz (1MHz offset), 245.76MHz clock
- Integrated phase noise of 61fs RMS typical (12kHz–20MHz)
- Dual-PLL architecture
- First PLL stage with external VCXO for clock jitter attenuation
- Second PLL with internal FemtoClockNG PLL: 2457.6MHz
- Five output channels with a total of 15 outputs
- Configurable integer clock frequency dividers
- Low-power LVPECL/LVDS outputs support configurable signal amplitude, DC and AC coupling, and LVPECL, LVDS line terminations techniques
- Phase delay circuits
- Redundant input clock architecture with two inputs
- SYSREF generation modes include internal and external trigger mode for JESD204B/C
- Supply voltage: 3.3V
- SPI interface, 3/4 wire configurable