Overview

The IDT5V41315 is a PCIe Gen1/2/3 clock synthesizer suitable for use in both Common-Clocked and Separate Reference clock with No Spread (SRNS) timing architectures. The IDT5V41315 uses a 25MHz input to generate 4 different output frequencies. The output frequency is selectable via select pins.

5V41315 Block Diagram
5V41315 Pinout Diagrams
5V41315 Block Diagram
5V41315 Pinout Diagrams
  • 16-pin TSSOP or VFQFPN package; small board footprint
  • Outputs can be terminated to LVDS; can drive a wider variety of devices
  • OE control pin; greater system power management
  • Industrial temperature range available; supports demanding embedded applications
  • Cycle-to-cycle jitter: 80ps
  • Output-to-output skew: <50 ps
  • PCIe Gen2 phase jitter: <3.0ps RMS (Common Clock)
  • PCIe Gen3 phase jitter: <1.0ps RMS (Common Clock)
  • Low Phase Noise: 12KHz to 20MHz <6ps RMS

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    5V41315NLGI
    circleObsolete
    memory
    view_in_ar
    		VFQFPN 16 I Yes Tray
    5V41315NLGI8
    circleObsolete
    memory
    view_in_ar
    		VFQFPN 16 I Yes Reel
    5V41315PGGI
    circleObsolete
    memory
    view_in_ar
    		TSSOP 16 I Yes Tube
    5V41315PGGI8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 16 I Yes Reel
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    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview