The IDT8V89317 is used to frequency synchronize equipment with an Ethernet connected reference or with a GPS based 1PPS reference; its integrated DCO (Digitally Controlled Oscillator) can be controlled by an external IEEE 1588 clock recovery servo to synthesize IEEE 1588-based clocks. The IDT8V89317 ultra-low jitter output clocks can be used to directly time 10 Gigabit Ethernet PHYs and QSGMII devices.


  • Digital PLL synchronizes with GPS or Ethernet connected synchronization sources
  • DPLL bandwidth is selectable to be 15 mHz or 1.2 Hz
  • DPLL holdover accuracy is 1.1X10-5 ppm
  • Input references are monitored for frequency offset and activity; DPLL holdover, free run and hitless reference switching can be forced by the host processor or can be automatically controlled by an internal state machine
  • Internal DCO has resolution of 0.01105 ppb and can be controlled by an external processor via I2C interface for IEEE 1588 clock generation
  • Two Analog PLLs for jitter attenuation and frequency translation
  • Jitter generation <0.3ps RMS (10 kHz to 20 MHz), meets jitter requirements of leading PHYs supporting 10GBASE-R, QSGMII and XAUI
  • IN1, IN2 and IN3 accept single ended reference clocks whose frequencies can be 1PPS (1 Hz), 25 MHz, 125 MHz or 156.25 MHz
  • OUT1 and OUT2 output differential clocks with frequencies of 125 MHz or 156.25 MHz
  • OUT3 outputs a differential clock with frequency of 322.265625 MHz or 644.53125 MHz
  • OUT4 outputs a free-running LVCMOS clock with frequency of 25 MHz

Product Options

Part Number Part Status Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active C Yes Tray
Active C Yes Reel


Title language Type Format File Size Date
Datasheets & Errata
8V89317 Datasheet Datasheet PDF 637 KB
8V89317 Short Form Datasheet Short Form Datasheet PDF 246 KB
User Guides & Manuals
8V89317 Device Driver API Reference Manual Manual - Software PDF 6.00 MB
82V391x / 8V893xx WAN PLL Device Families – Device Driver User's Guide Manual - User Reference PDF 232 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages Product Change Notice PDF 93 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
Timing Fabric for Communications Equipment Overview Overview PDF 263 KB


Title language Type Format File Size Date
8V89317 Device Driver Package (source only, tarball) Software TGZ 160 KB
8V89317 Device Driver Package (source only, zip) Software ZIP 275 KB
8V89317 BSDL File Model - BSDL BSD 15 KB
8V89317 IBIS File (zip) Model - IBIS ZIP 67 KB

Boards & Kits

Part Number Title Type Company
8EBV89317 Evaluation Board 8EBV89317 for Industrial Automation and Power Systems - 10G Ethernet PLL and IEEE 1588 Synthesizer Evaluation Renesas