The 8A34046 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) and Optical Transport Network (OTN) is a highly integrated timing device with four Digital PLL (DPLL) channels and four Digitally Controlled Oscillator (DCO) channels. The device integrates the timing blocks necessary to implement the SETS function as described in ITU-T G.8264.

The 8A34046 DPLL channels can be configured to comply with ITU-T G.8262 and G.8262.1 or as jitter attenuators; they can also be configured as DCOs. The DCO channels can be connected to a DPLL channel to supply additional outputs and frequencies for that DPLL; alternatively they can be controlled by external software or they can free run based on the local oscillator. The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.


  • Four independent Digital PLLs (DPLLs) and four independent Digitally Controlled Oscillators (DCOs)
  • DPLLs comply with ITU-T G.8262 and G.8262.1 for SyncE and OTN
  • DPLLs lock to any frequency from 1kHz to 1GHz
  • DPLLs / DCOs generate any frequency from 0.5Hz to 1GHz
  • Jitter output below 150fs RMS (typical)
  • Supports up to 4 differential; or 8 single-ended reference clock inputs
  • Supports up to 12 differential outputs; or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

Product Options

Part Number Part Status Temp. Range Carrier Type Buy Sample
Active 0 to 70°C Tray
Active 0 to 70°C Reel
Active 0 to 70°C Reel


Title language Type Format File Size Date
Datasheets & Errata
8A34046 Datasheet Datasheet PDF 1.93 MB
8A34046E-001 Datasheet Addendum Datasheet PDF 185 KB
8A3xxxx Firmware Version v4.8.7 Errata Notice Errata PDF 38 KB
User Guides & Manuals
8A3xxxx Firmware Version v4.9.1 Release Notes Guide PDF 213 KB
8A3xxxx Firmware Version v4.8.7 Release Notes Guide PDF 143 KB
8A3xxxx Family Programming Guide (v4.8.7) Guide PDF 2.33 MB
ClockMatrix GUI Step-by-Step User Guide Guide PDF 4.98 MB
8A34xxx 72QFN EVK User Manual Manual - Eval Board PDF 2.03 MB
Application Notes & White Papers
ClockMatrix Oscillator Compensation Application Note PDF 231 KB
AN-807 Recommended Crystal Oscillators for Network Synchronization Application Note PDF 148 KB
AN-1010 ClockMatrix Time-to-Digital Converter Application Note PDF 1.57 MB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 Application Note PDF 390 KB
Translating Non-Integer Frequencies with ClockMatrix Application Note PDF 880 KB
Auto-Alignment of Outputs Application Note PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback Application Note PDF 155 KB
ClockMatrix Firmware Update through Serial Port and EEPROM v1.0 Application Note PDF 739 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment Application Note PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy Application Note PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 324 KB
PCN# : 210012 Firmware Update for Clock Matrix Family of Jitter Attenuators and Clock Synchronizers Product Change Notice PDF 113 KB
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 Product Change Notice PDF 301 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products Product Change Notice PDF 435 KB
8A3x0xx Schematic Checklist (v1.23) Miscellaneous XLSX 318 KB
ClockMatrix Family Overview Overview PDF 285 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
ClockMatrix 72-QFN (12 Output) Reference Schematic Schematic PDF 98 KB


Title language Type Format File Size Date
Timing Commander Installer (v1.16.4) Software ZIP 19.79 MB
ClockMatrix Register Header Files v4.8.7 Software ZIP 278 KB
ClockMatrix Firmware (v4.8.7) Trigger Registers, v1.1 Software ZIP 73 KB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.2, FWv4.8.7) Software ZIP 47.13 MB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 Software ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 Software ZIP 177 KB
8A34046 BSDL Model Model - BSDL ZIP 2 KB
8A340xx ClockMatrix IBIS Model v1.13 Model - IBIS ZIP 2.55 MB