Overview
Description
The 9DB403 is compatible the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC clocks. The 9DB403 is driven by a differential input pair from a CK409/CK410/CK505 main clock generator.
Features
- 4- 0.7 V HCSL differential output pairs
- Phase jitter: PCIe Gen2 < 3.1 ps rms
- Phase jitter: PCIe Gen1 < 86 ps peak to peak
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- 50-100 MHz operation in PLL mode
- 50-400 MHz operation in Bypass mode
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| SSOP | 28 | I | Yes | Tube | 1 | 3.035 | Get Samples, | |
| SSOP | 28 | I | Yes | Reel | 1 | |||
| SSOP | 28 | C | Yes | Tube | 1 | 2.833 | Get Samples, | |
| SSOP | 28 | C | Yes | Reel | 1 | 2.833 | ||
| TSSOP | 28 | I | Yes | Tube | 1 | 2.559 | Get Samples, | |
| TSSOP | 28 | I | Yes | Reel | 1 | 2.559 | ||
| TSSOP | 28 | C | Yes | Tube | 1 | 2.39 | Get Samples, | |
| TSSOP | 28 | C | Yes | Reel | 1 |
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Videos & Training
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List