Renesas Electronics Corporation
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74SSTUBF32866B

Obsolete

25-Bit Configurable Registered Buffer for DDR2

Overview

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

Documentation

Featured Documentation
Type Title Date
Datasheet
74SSTUBF32866B Datasheet
PDF 710 KB
End Of Life Notice
PLC# : 220001-R1 End-of-Life (EOL) Process on Select Part Numbers
PDF 938 KB
End Of Life Notice
PLC# : 220001 End-of-Life (EOL) Process on Select Part Numbers
PDF 909 KB
Product Change Notice
PCN# : PCN20001 Add Alternate Substrate Supplier for Select CABGA and FCBGA Packages
PDF 113 KB
Product Change Notice
PCN# : A1609-02 Alternate Site at OSET Taiwan on Select Packages
PDF 30 KB
Product Change Notice
PCN#: A1309-03 Additional Assembly Sources
PDF 398 KB
6 items

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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