概要
説明
The 9FGU0831 is a member of IDT's 1.5 V Ultra-Low-Power PCIe clock family. The device has 8 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses.
特長
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LP-HCSL outputs; save 16 resistors compared to standard PCIe devices
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50 mW typical power consumption; reduced thermal concerns
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Outputs can optionally be supplied from any voltage between 1.05 and 1.5 V; maximum power savings
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OE# pins; support DIF power management
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Programmable Slew rate for each output; allows tuning for various line lengths
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Programmable output amplitude; allows tuning for various application environments
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DIF outputs blocked until PLL is locked; clean system start-up
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Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
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External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
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Configuration can be accomplished with strapping pins; SMBus interface not required for device control
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3.3 V tolerant SMBus interface works with legacy controllers
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Space saving 6x6 mm 48-pin VFQFPN; minimal board space
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Selectable SMBus addresses; multiple devices can easily share an SMBus segment.
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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製品選択
適用されたフィルター
サポート
ビデオ&トレーニング
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List
