パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG72 |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
製品スペック
| Pkg. Type | VFQFPN |
| Lead Count (#) | 72 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| Country of Assembly | CHINA |
| Country of Wafer Fabrication | TAIWAN |
| Advanced Features | Hitless Reference Switching, External Sync Input |
| App Jitter Compliance | GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.8262. ITU-T G.813, ITU-T G.783 |
| Application | Port Synchronizer |
| Channels (#) | 2 |
| Core Voltage (V) | 3.3 |
| Diff. Inputs | 0 |
| Diff. Outputs | 2 |
| Input Freq (MHz) | 1.0E-6 - 156.25 |
| Input Freq Range Type | TDM, DS1, E1, SONET/SDH, Ethernet, Sync Pulse |
| Input Type | LVPECL, LVDS, LVCMOS |
| Inputs (#) | 4 |
| Length (mm) | 10 |
| MOQ | 168 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 6 |
| Output Freq Range (MHz) | 1.0E-6 - 644.531 |
| Output Freq Range Type | 1PPS (1 Hz), TDM, DS1, E1, DS2, E3, DS3, 100BASE-T, STM-1/OC-3, STM-4/OC-12, 1000BASE-T/X |
| Output Skew (ps) | 150 |
| Output Type | LVPECL, LVDS, LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 6 |
| Package Area (mm²) | 100 |
| Pb Free Category | e3 Sn |
| Phase Jitter Typ RMS (ps) | 0.8 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Price (USD) | $38.77327 |
| Prog. Clock | Yes |
| Prog. Interface | I2C, Serial, JTAG |
| Qty. per Carrier (#) | 168 |
| Qty. per Reel (#) | 0 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
| 掲載 | No |
82V3395 に関するリソース
説明
The 82V3395 is an integrated, single-chip solution for the Synchronous Equipment Timing applications in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device supports several types of input clock sources: recovered clock from Synchronous Ethernet, STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The device consists of 2 DPLL+APLL paths. The two path lock independently from each other. An input clock is automatically or manually selected for both path. Both paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. There are 2 high performance APLLs that can be used for low jitter SONET and Ethernet Clocks The device provides programmable DPLL bandwidths: 18 Hz, 35 Hz, 70 Hz and 560 Hz. A stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. All the read/write registers are accessed through a microprocessor interface. The device supports I2C and serial microprocessor interface modes.