特長
- Supports clock frequencies up to 100MHz
- Fast access times of 6.5ns
- Free-running CLKA and CLKB may be asynchronous or coincident
- Mailbox bypass register for each FIFO
- Programmable Almost-Full and Almost-Empty flags
- Select IDT Standard timing or First Word Fall Through timing
- Available in 132-pin PQFP and 120-pin TQFP packages
- Pin compatible to the lower density parts, IDT72V36x2
- Industrial temperature range (–40C to +85C) is available
72V3652 - Block Diagram
説明
The 72V3652 is a 3.3V CMOS Bidirectional SyncFIFO (clocked) memories. Two independent 2K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
