クロック&タイミング

概要

The 9ZML1252E is a second generation 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance specifications and is backwards compatible to the 9ZML1232B. It utilizes Low Power HCSL-compatible outputs to reduce power consumption and termination resistors. It is suitable for PCI-Express Gen1-4 or QPI/UPI applications, and provides 2 configurable low-drift I2O settings, one for each input channel, to allow I2O tuning for various topologies.

9ZML1252E - Block Diagram
9ZML1252E - Pinout
9ZML1252E - Block Diagram
9ZML1252E - Pinout
  • 2 configurable low-drift I2O delays up to 2.9ns; maintain transport delay for various topologies
  • LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
  • 9 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Separate VDDIO for outputs; allows maximum power savings
  • PLL or Bypass Mode; PLL can dejitter incoming clock
  • Hardware or software-selectable PLL BW; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • SMBus interface; software can modify device settings without hardware changes
  • 10 x 10 mm 72-QFN package; small board footprint
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ドキュメント

タイトル 分類 日付
9ZML1232E-9ZML1252E Datasheet
PDF382 KB
データシート
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
アプリケーションノート
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5
PDF244 KB
アプリケーションノート
AN-975 Cascading PLLs
PDF255 KB
アプリケーションノート
AN-828 Termination - LVPECL
PDF322 KB
アプリケーションノート
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs
PDF480 KB
アプリケーションノート
AN-879 Low-Power HCSL vs Traditional HCSL
PDF235 KB
アプリケーションノート
AN-844 Termination - AC Coupling Clock Receivers
PDF170 KB
アプリケーションノート
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
アプリケーションノート
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
アプリケーションノート
AN-815 Understanding Jitter Units
PDF565 KB
アプリケーションノート
AN-805 Recommended Ferrite Beads
PDF121 KB
アプリケーションノート
AN-808 PCI Express/HCSL Termination
PDF137 KB
アプリケーションノート
PCI Express Timing Solutions Overview
PDF2.40 MB
概要
IDT Clock Generation Overview
PDF1.83 MB
概要
PCN# : TP1910-03-R1 Update the Cut-off Date Code
PDF163 KB
製品変更通知
PCN# : TP1910-03 Top Metal Change
PDF158 KB
製品変更通知
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility
PDF983 KB
製品変更通知
 
info: For device-specific or order-specific documentation, submit a support request.

設計・開発

ボード＆キット

9ZXL1951 - Evaluation Board (top)

EVK9ZXL1951D

Evaluation
ご購入

Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

The evaluation board is designed to help the customer evaluate the 9ZXL1951D. The device is programmable through an  SMBus interface. The user guide details the board set and connection, as well as the companion GUI installation for communicating to the device. The board has a self-contained USB to SMBus interface.
主要ドキュメント:
9ZXL1951D PCIe Clock Generator Evaluation Board User Guide

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ビデオ&トレーニング

PCIe Gen5 Clock Buffers

Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page. 

Video List