Overview
Description
The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.
Features
- 6 - 0.7 V current mode differential HCSL output pairs
- Cycle-to-cycle jitter < 50 ps
- Output-to-output skew < 50 ps
- PCIe Gen3 phase jitter < 1.0 ps RMS
- OE# pins/Suitable for Express Card applications
- PLL or bypass mode/PLL can dejitter incoming clock
- Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
- Spread Spectrum Compatible/tracks spreading input clock for low EMI
- SMBus Interface/unused outputs can be disabled
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
| TSSOP | 28 | I | Yes | Tube | 1 | 3.144 | Get Samples, | |
| TSSOP | 28 | I | Yes | Reel | 1 | 3.379 | ||
| TSSOP | 28 | C | Yes | Tube | 1 | 5.158 | Get Samples, | |
| TSSOP | 28 | C | Yes | Reel | 1 | 2.971 |
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Videos & Training
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
News & Blog Posts
| Blog Post | Apr 14, 2022 | ||
| Blog Post | May 22, 2018 | ||
| News | Apr 30, 2018 |
