Overview

Description

The 72V82 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

Features

  • Equivalent to two 72V02 1K x 9 FIFOs
  • Asynchronous and simultaneous read and write
  • Status Flags: Empty, Half-Full, Full
  • Auto-retransmit capability
  • Available in 56 pin TSSOP
  • Industrial temperature range (–40C to +85C) is available

Documentation

Document title Document type
Type
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PDF 166 KB Datasheet
PDF 1.11 MB End Of Life Notice
PDF 645 KB End Of Life Notice
PDF 123 KB Guide
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27 items

Design & Development

Software & Tools

Software Downloads

Software title Software type Type Date Date
PDF 1.11 MB End Of Life Notice
PDF 645 KB End Of Life Notice
2 items

Models

Models

Title Type Type Date Date
ZIP 10 KB Model - IBIS
TAR 32 KB Model - SPICE
2 items