Lead Count (#) | 8 |
Pkg. Type | TSSOP |
Pkg. Code | DVG8 |
Pitch (mm) | 0.65 |
Pkg. Dimensions (mm) | 3.0 x 3.0 x 0.97 |
Pb (Lead) Free | Yes |
ECCN | NLR |
HTSUS | 8542390000 |
Moisture Sensitivity Level (MSL) | 3 |
Pkg. Type | TSSOP |
Lead Count (#) | 8 |
Pb (Lead) Free | Yes |
Carrier Type | Tube |
Additive Phase Jitter Typ RMS (fs) | 250 |
Additive Phase Jitter Typ RMS (ps) | 0.25 |
Core Voltage (V) | 3.3 |
Function | Buffer |
Input Freq (MHz) | 0 - 1000 |
Input Type | LVCMOS |
Inputs (#) | 2 |
Length (mm) | 3.0 |
MOQ | 200 |
Moisture Sensitivity Level (MSL) | 3 |
Output Banks (#) | 2 |
Output Freq Range (MHz) | 0 - 1000 |
Output Skew (ps) | 100 |
Output Type | LVPECL |
Output Voltage (V) | 3.3 |
Outputs (#) | 2 |
Package Area (mm²) | 9.0 |
Pb Free Category | e3 Sn |
Pitch (mm) | 0.65 |
Pkg. Dimensions (mm) | 3.0 x 3.0 x 0.97 |
Qty. per Carrier (#) | 96 |
Qty. per Reel (#) | 0 |
Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
Tape & Reel | No |
Temp. Range | 0 to 70°C |
Thickness (mm) | 0.97 |
Width (mm) | 3.0 |
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate design are ideal for clock translation applications.