Overview
Description
The 8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew characteristics make the 8531-01 ideal for high performance workstation and server applications.
Features
- Nine differential 3.3V LVPECL outputs
- Selectable differential CLK, nCLK or LVPECL clock inputs
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
- Maximum output frequency: 500MHz
- Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
- Additive phase jitter, RMS: 0.17ps (typical)
- Output skew: 50ps (maximum)
- Part-to-part skew: 250ps (maximum)
- Propagation delay: 2ns (maximum)
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- Industrial Temperature information available upon request
Comparison
Applications
Design & Development
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FAQs
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In the 85310I family of ICs (85310I-01, -11, -21), what happens if we leave the CLK_SEL and the CLK_EN pins as a No Connect (floating) ?
When the CLK_SEL and CLK_EN pins are left open (floating), the internal pull-up and pull-down resistors will pull these pins to their default levels. For other questions not addressed by the knowledge base, please submit a technical support request.
Oct 31, 2016 -
In the 85310I family of ICs (85310I-01, -11, -21), after the CLK_SEL is asserted, how long does it take for the outputs to synchronize with the selected CLK input ?
The outputs will synchronize to the newly selected clock inputs within one clock cycle. For other questions not addressed by the knowledge base, please submit a technical support request.
Oct 31, 2016