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Low Skew,1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer

Package Information

Lead Count (#) 32
Pkg. Code PRG32
Pitch (mm) 0.8
Pkg. Type TQFP
Pkg. Dimensions (mm) 7.0 x 7.0 x 1.4

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

Product Attributes

Lead Count (#) 32
Carrier Type Reel
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 2000
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range 0 to 70°C
Additive Phase Jitter Typ RMS (fs) 30
Additive Phase Jitter Typ RMS (ps) 0.03
Core Voltage (V) 3.3, 2.5
Diff. Input Signaling 3.3, 2.5
Function Buffer, Multiplexer
Input Freq (MHz) 0 - 250
Input Type LVCMOS, SSTL, CML, LVPECL
Inputs (#) 2
Length (mm) 7
MOQ 2000
Multiply/Divide Value 1.00000
Operating Freq 0.00000
Output Banks (#) 1
Output Freq Range (MHz) 0 - 250
Output Signaling LVCMOS
Output Skew (ps) 200
Output Type LVCMOS
Output Voltage (V) 3.3, 2.5
Outputs (#) 18
Package Area (mm²) 49.0
Pitch (mm) 0.8
Pkg. Dimensions (mm) 7.0 x 7.0 x 1.4
Pkg. Type TQFP
Pre Divider 0
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Supply Voltage (V) 3.3 - 3.3
Tape & Reel Yes
Thickness (mm) 1.4
Width (mm) 7

Description

The 83940D is a low skew, 1-to-18 LVPECL-to- LVCMOS/LVTTL Fanout Buffer. The 83940D has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The 83940D is characterized at full 3.3V and 2.5V or mixed3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83940D ideal for those clock distribution applications demanding well defined performance and repeatability.